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ECE elective: Digital IC Design with Open Tools

MOS devices, inverters, logic styles and sizing, timing and power, and a cell laid out in an open chip process.

MOS devices, inverters, logic styles and sizing, timing and power, and a cell laid out in an open chip process. Free courses and textbooks, a self-check for every unit, and a build you can rerun, confirmed by people. An elective of the Varsity Curriculum: Electrical & Computer Engineering.

Part of: Electrical & Computer Eng. · Proves for: UG

0 required outcomes14 weeksCredential on completion

Path outcomes

How this is verified: 4 are checked automatically, then confirmed by one person.

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ECE elective: Digital IC Design with Open Tools

Elective: Digital IC Design with Open Tools.

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4 milestones

  1. 1MOS devices and the CMOS inverter
  2. 2Logic styles, sizing and sequential circuits
  3. 3Interconnect, clocking and memory
  4. 4Design, simulate and lay out a NAND cell in SKY130

Resources for this path

No affiliate links. No sponsored placements.

Free, open process design kit for a real 130 nm chip process.

Free, open-source chip layout editor with design-rule checks.

Free layout-versus-schematic (LVS) checker for Magic layouts.

Free schematic editor for ngspice simulations.

Free, open-source SPICE circuit simulator.

Free RTL-to-layout flow for the SKY130 process.