Milestone map
Milestone map
4 milestones
MOS devices and the CMOS inverter
about 3 weeks (about 12 hrs/week)
Read the 6.374 lecture notes on MOS models and the inverter's static and dynamic behaviour. Then solve 6.374 problem set 1. Self-check: MIT 6.374 problem sets 1–5 with solutions. Free tools only.
Proof required
Link the public repo with 6.374 problem set 1 written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Device regions are stated for each operating point.
- Inverter delay and switching threshold are derived, then simulated.
- Answers match the published solutions, and misses are reworked.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of 6.374 problem set 1, with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 13: Digital IC Design with Open Tools, unit 1: MOS devices and the CMOS inverter Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Device regions are stated for each operating point.
- Inverter delay and switching threshold are derived, then simulated.
- Answers match the published solutions, and misses are reworked.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Logic styles, sizing and sequential circuits
about 3 weeks (about 12 hrs/week)
Read the 6.374 notes on static, ratioed, pass-transistor and dynamic logic, logical effort, and latches and flip-flops. Then solve 6.374 problem sets 2–4. Self-check: MIT 6.374 problem sets 1–5 with solutions. Free tools only.
Proof required
Link the public repo with 6.374 problem sets 2–4 written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Gate sizes come from logical effort, with the path effort shown.
- Setup and hold are worked out for each flip-flop.
- Answers match the published solutions, and misses are reworked.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of 6.374 problem sets 2–4, with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 13: Digital IC Design with Open Tools, unit 2: Logic styles, sizing and sequential circuits Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Gate sizes come from logical effort, with the path effort shown.
- Setup and hold are worked out for each flip-flop.
- Answers match the published solutions, and misses are reworked.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Interconnect, clocking and memory
about 3 weeks (about 12 hrs/week)
Read the 6.374 notes on interconnect, clocking, power and memory. Then solve 6.374 problem set 5. Self-check: MIT 6.374 problem sets 1–5 with solutions. Free tools only.
Proof required
Link the public repo with 6.374 problem set 5 written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Wire delay uses an RC model with stated parasitics.
- Clock skew and jitter are included in every timing check.
- Answers match the published solution, and misses are reworked.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of 6.374 problem set 5, with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 13: Digital IC Design with Open Tools, unit 3: Interconnect, clocking and memory Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Wire delay uses an RC model with stated parasitics.
- Clock skew and jitter are included in every timing check.
- Answers match the published solution, and misses are reworked.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Design, simulate and lay out a NAND cell in SKY130
about 3 weeks (about 12 hrs/week)
Make a two-input NAND standard cell in the SkyWater SKY130 process: Xschem schematic, ngspice simulation and Magic layout. Size the transistors by hand for equal rise and fall delay. Predict the 50%-to-50% delay driving four copies of your cell (FO4) and the switching energy C·VDD² at 1.8 V. Simulate the schematic, draw the layout in Magic, and pass DRC in Magic and LVS in Netgen. Re-simulate with extracted parasitics and fill a predicted-vs-simulated table.
Proof required
Link the public repo with the code or design files, the one command that reruns it, and the predicted-vs-simulated table, and a README that says how to rerun it and what limits the result.
What gets checked
- The layout passes DRC and LVS, with the reports in the repo.
- Pre- and post-layout delay and energy are compared with the hand predictions.
- The gap after extraction is explained.
Common mistakes
- A result that nobody else can rerun from the repo.
- A table with no explanation of the gaps.
Powstik Guide
A two-input NAND standard cell in the SkyWater SKY130 process: Xschem schematic, ngspice simulation and Magic layout, in a public repo.
Steps
- Write down what you expect before you start.
- Size the transistors by hand for equal rise and fall delay. Predict the 50%-to-50% delay driving four copies of your cell (FO4) and the switching energy C·VDD² at 1.8 V. Simulate the schematic, draw the layout in Magic, and pass DRC in Magic and LVS in Netgen. Re-simulate with extracted parasitics and fill a predicted-vs-simulated table.
- Fill the predicted-vs-measured table.
- Explain every gap with a cause someone can check.
- Write the README and ask someone who knows the subject to rerun it.
Template
README ECE 13: Digital IC Design with Open Tools — Design, simulate and lay out a NAND cell in SKY130 What I expected: How to rerun it: Predicted vs measured: Why they differ:
What gets sent back
- It does not run from the repo.
- No predicted-vs-measured table.
Resources
Foundationstart here
What a verifier looks for
- The layout passes DRC and LVS, with the reports in the repo.
- Pre- and post-layout delay and energy are compared with the hand predictions.
- The gap after extraction is explained.
- Rerun it from the repo: does it run, and do the numbers match the table?
You'll sign in first, then come straight back here.