Milestone map
Milestone map
4 milestones
Information, the digital abstraction and CMOS
about 3 weeks (about 12 hrs/week)
Work through 6.004 topics 1–3 (videos, slides and worksheets). Then solve the 6.004 worksheets for topics 1 (Basics of Information), 2 (The Digital Abstraction) and 3 (CMOS). Self-check: MIT 6.004 worksheet with answers: CMOS. Free tools only.
Proof required
Link the public repo with the 6.004 worksheets for topics 1 (Basics of Information), 2 (The Digital Abstraction) and 3 (CMOS) written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Entropy and encoding answers show the working.
- Noise margins are read from a voltage transfer curve.
- Worksheet answers are checked against the published answers, and misses are reworked.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of the 6.004 worksheets for topics 1 (Basics of Information), 2 (The Digital Abstraction) and 3 (CMOS), with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 3: Digital Systems, unit 1: Information, the digital abstraction and CMOS Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Entropy and encoding answers show the working.
- Noise margins are read from a voltage transfer curve.
- Worksheet answers are checked against the published answers, and misses are reworked.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Combinational logic in Verilog
about 3 weeks (about 12 hrs/week)
Work through 6.004 topic 4 and do the HDLBits combinational-logic problems. Then solve the 6.004 topic 4 worksheet and the HDLBits combinational-logic section. Self-check: MIT 6.004 worksheet with answers: Combinational Logic. Free tools only.
Proof required
Link the public repo with the 6.004 topic 4 worksheet and the HDLBits combinational-logic section written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Truth tables, Karnaugh maps and gate-level answers agree.
- Each HDLBits problem passes its simulation check.
- Worksheet answers are checked against the published answers.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of the 6.004 topic 4 worksheet and the HDLBits combinational-logic section, with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 3: Digital Systems, unit 2: Combinational logic in Verilog Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Truth tables, Karnaugh maps and gate-level answers agree.
- Each HDLBits problem passes its simulation check.
- Worksheet answers are checked against the published answers.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Sequential logic and finite state machines
about 3 weeks (about 12 hrs/week)
Work through 6.004 topics 5–8 and do the HDLBits sequential-logic and FSM problems. Then solve the 6.004 worksheets for topics 5 (Sequential Logic), 6 (Finite State Machines) and 7 (Performance Measures) and the HDLBits FSM section. Self-check: MIT 6.004 worksheet with answers: Finite State Machines. Free tools only.
Proof required
Link the public repo with the 6.004 worksheets for topics 5 (Sequential Logic), 6 (Finite State Machines) and 7 (Performance Measures) and the HDLBits FSM section written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- The minimum clock period and the hold-time constraint are checked for each register path.
- State diagrams and state tables match.
- Worksheet answers and HDLBits checks pass, and misses are reworked.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of the 6.004 worksheets for topics 5 (Sequential Logic), 6 (Finite State Machines) and 7 (Performance Measures) and the HDLBits FSM section, with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 3: Digital Systems, unit 3: Sequential logic and finite state machines Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- The minimum clock period and the hold-time constraint are checked for each register path.
- State diagrams and state tables match.
- Worksheet answers and HDLBits checks pass, and misses are reworked.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
A UART transmitter in Verilog with a passing testbench
about 3 weeks (about 12 hrs/week)
Make a UART transmitter (idle high, 1 start bit, 8 data bits sent least significant bit first, no parity, 1 stop bit, parameterised baud rate) written in Verilog, with a self-checking testbench. Write the FSM and a testbench that sends known bytes and checks every bit time against the expected waveform. Predict the clock cycles per bit, the frame time and the baud-rate error of your divider, then fill a predicted-vs-simulated table. Simulate with Icarus Verilog or Verilator, view it in GTKWave, and synthesise with Yosys to report the cell count. Optional, costs money: an FPGA board to run it on real pins. Safety: 12 V DC or less, from AA, AAA or 9 V batteries or USB only. Never mains power, never a lithium-polymer pack or loose lithium cell, and never a home-made battery charger. Wear eye protection when soldering or cutting leads. Under 18? Use the simulator, or build and solder with an adult present.
Proof required
Link the public repo with the Verilog, the testbench, the one command that runs it, the passing output, a waveform screenshot and the predicted-vs-simulated table, and a README that says how to rerun it and what limits the result.
What gets checked
- One documented command runs the testbench; it prints PASS, and a wrong byte or baud rate makes it print FAIL.
- The predicted-vs-simulated table gives cycles per bit, frame time and baud-rate error, matching the waveform.
- The Yosys cell-count report and a GTKWave screenshot of one full frame are in the repo.
Common mistakes
- A result that nobody else can rerun from the repo.
- A table with no explanation of the gaps.
Powstik Guide
A UART transmitter (idle high, 1 start bit, 8 data bits sent least significant bit first, no parity, 1 stop bit, parameterised baud rate) written in Verilog, with a self-checking testbench, in a public repo.
Steps
- Write down what you expect before you start.
- Write the FSM and a testbench that sends known bytes and checks every bit time against the expected waveform. Predict the clock cycles per bit, the frame time and the baud-rate error of your divider, then fill a predicted-vs-simulated table. Simulate with Icarus Verilog or Verilator, view it in GTKWave, and synthesise with Yosys to report the cell count.
- Fill the predicted-vs-measured table.
- Explain every gap with a cause someone can check.
- Write the README and ask someone who knows the subject to rerun it.
Template
README ECE 3: Digital Systems — A UART transmitter in Verilog with a passing testbench What I expected: How to rerun it: Predicted vs measured: Why they differ:
What gets sent back
- It does not run from the repo.
- No predicted-vs-measured table.
- Mains power, a lithium pack or loose cell, a home-made charger, or more than 12 V DC.
Resources
Foundationstart here
What a verifier looks for
- One documented command runs the testbench; it prints PASS, and a wrong byte or baud rate makes it print FAIL.
- The predicted-vs-simulated table gives cycles per bit, frame time and baud-rate error, matching the waveform.
- The Yosys cell-count report and a GTKWave screenshot of one full frame are in the repo.
- Rerun it from the repo: does it run, and do the numbers match the table?
- The build uses 12 V DC or less from AA, AAA or 9 V batteries or USB; nothing touches mains, and there is no lithium pack, loose cell or home-made charger.
You'll sign in first, then come straight back here.
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