Milestone map
Milestone map
4 milestones
Instruction sets, assembly, procedures and stacks
about 3 weeks (about 12 hrs/week)
Work through 6.004 topics 9–12. 6.004 (2017) uses the Beta instruction set; map each idea to RV32I in the RISC-V spec. Then solve the 6.004 worksheets for topics 9 (Designing an Instruction Set) and 12 (Procedures and Stacks). Self-check: MIT 6.004 worksheet with answers: Procedures and Stacks. Free tools only.
Proof required
Link the public repo with the 6.004 worksheets for topics 9 (Designing an Instruction Set) and 12 (Procedures and Stacks) written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Assembly is traced instruction by instruction.
- Stack frames are drawn for each call.
- Worksheet answers are checked against the published answers, and misses are reworked.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of the 6.004 worksheets for topics 9 (Designing an Instruction Set) and 12 (Procedures and Stacks), with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 9: Computer Architecture, unit 1: Instruction sets, assembly, procedures and stacks Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Assembly is traced instruction by instruction.
- Stack frames are drawn for each call.
- Worksheet answers are checked against the published answers, and misses are reworked.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Building and pipelining a processor
about 3 weeks (about 12 hrs/week)
Work through 6.004 topics 13 and 15; read the 6.823 notes on pipelining. Then solve the 6.004 worksheets for topics 13 (Building the Beta) and 15 (Pipelining the Beta). Self-check: MIT 6.004 worksheet with answers: Pipelining the Beta. Free tools only.
Proof required
Link the public repo with the 6.004 worksheets for topics 13 (Building the Beta) and 15 (Pipelining the Beta) written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Datapath control signals are listed for each instruction.
- Hazards are found and resolved (stall, bypass or annul).
- Worksheet answers are checked against the published answers.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of the 6.004 worksheets for topics 13 (Building the Beta) and 15 (Pipelining the Beta), with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 9: Computer Architecture, unit 2: Building and pipelining a processor Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Datapath control signals are listed for each instruction.
- Hazards are found and resolved (stall, bypass or annul).
- Worksheet answers are checked against the published answers.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
Caches, virtual memory and interrupts
about 3 weeks (about 12 hrs/week)
Work through 6.004 topics 14, 16 and 18. Then solve the 6.004 worksheets for topics 14 (Caches), 16 (Virtual Memory) and 18 (Devices and Interrupts). Self-check: MIT 6.004 worksheet with answers: Caches and the Memory Hierarchy. Free tools only.
Proof required
Link the public repo with the 6.004 worksheets for topics 14 (Caches), 16 (Virtual Memory) and 18 (Devices and Interrupts) written up (a typeset PDF, LaTeX source or notebook), and show the self-check: which answers matched and how you fixed the ones that did not.
What gets checked
- Hit rates and average access times are computed for each cache.
- Address translation is traced through the page table.
- Worksheet answers are checked against the published answers.
Common mistakes
- Answers copied from a solution with no working.
- Missing units, or a sign or factor-of-2π slip left unexplained.
Powstik Guide
A public write-up of the 6.004 worksheets for topics 14 (Caches), 16 (Virtual Memory) and 18 (Devices and Interrupts), with the self-check shown.
Steps
- Study the linked course material.
- Solve the problems on your own first.
- Check them against the self-check and rework the misses.
- Typeset the write-up (LaTeX or a notebook) in a public repo.
- Ask someone who knows the subject to check it.
Template
README ECE 9: Computer Architecture, unit 3: Caches, virtual memory and interrupts Problems: Self-check result (matched / reworked): What I got wrong first and why:
What gets sent back
- No working shown.
- The self-check result is missing.
Resources
Foundationstart here
Depthgo deeper
What a verifier looks for
- Hit rates and average access times are computed for each cache.
- Address translation is traced through the page table.
- Worksheet answers are checked against the published answers.
- Is the engineering right, not just the final number?
You'll sign in first, then come straight back here.
A pipelined RISC-V core with a passing testbench
about 3 weeks (about 12 hrs/week)
Make a five-stage pipelined RISC-V core (a documented subset of RV32I) in Verilog, with a testbench that runs test programs. Implement fetch, decode, execute, memory and write-back with forwarding, load-use stalls and branch flushes. Assemble test programs with the free GNU RISC-V toolchain and record their known final register and memory values. Predict each program's CPI by counting stalls and flushes, then run them in Icarus Verilog or Verilator and fill a predicted-vs-simulated table. Optional, costs money: an FPGA board. Safety: 12 V DC or less, from AA, AAA or 9 V batteries or USB only. Never mains power, never a lithium-polymer pack or loose lithium cell, and never a home-made battery charger. Wear eye protection when soldering or cutting leads. Under 18? Use the simulator, or build and solder with an adult present.
Proof required
Link the public repo with the Verilog, the testbench, the one command that runs it, the passing output, a waveform screenshot and the predicted-vs-simulated table, and a README that says how to rerun it and what limits the result.
What gets checked
- One documented command runs every program and prints PASS or FAIL for each; a deliberately wrong expected value prints FAIL.
- Tests cover a forwarding case, a load-use stall, a taken branch and a write to x0.
- Predicted CPI from counted stalls and flushes matches the simulated cycle count for each program.
Common mistakes
- A result that nobody else can rerun from the repo.
- A table with no explanation of the gaps.
Powstik Guide
A five-stage pipelined RISC-V core (a documented subset of RV32I) in Verilog, with a testbench that runs test programs, in a public repo.
Steps
- Write down what you expect before you start.
- Implement fetch, decode, execute, memory and write-back with forwarding, load-use stalls and branch flushes. Assemble test programs with the free GNU RISC-V toolchain and record their known final register and memory values. Predict each program's CPI by counting stalls and flushes, then run them in Icarus Verilog or Verilator and fill a predicted-vs-simulated table.
- Fill the predicted-vs-measured table.
- Explain every gap with a cause someone can check.
- Write the README and ask someone who knows the subject to rerun it.
Template
README ECE 9: Computer Architecture — A pipelined RISC-V core with a passing testbench What I expected: How to rerun it: Predicted vs measured: Why they differ:
What gets sent back
- It does not run from the repo.
- No predicted-vs-measured table.
- Mains power, a lithium pack or loose cell, a home-made charger, or more than 12 V DC.
Resources
Foundationstart here
What a verifier looks for
- One documented command runs every program and prints PASS or FAIL for each; a deliberately wrong expected value prints FAIL.
- Tests cover a forwarding case, a load-use stall, a taken branch and a write to x0.
- Predicted CPI from counted stalls and flushes matches the simulated cycle count for each program.
- Rerun it from the repo: does it run, and do the numbers match the table?
- The build uses 12 V DC or less from AA, AAA or 9 V batteries or USB; nothing touches mains, and there is no lithium pack, loose cell or home-made charger.
You'll sign in first, then come straight back here.