6 weeks · 0 milestones
Design a digital logic system to implement a defined Boolean function or finite state machine. The system must be non-trivial — at minimum a 4-bit binary counter with enable and reset, an 8-to-1 multiplexer with documented truth table, or an equivalent sequential or combinational circuit. Required documentation: a complete logic diagram or HDL description, a truth table or state transition table, timing analysis identifying critical path and maximum clock frequency (for sequential circuits), and a documented test plan with at least 10 test vectors with expected and actual results. Preferred proof: an FPGA implementation or physical breadboard build with documented test results. Accessible alternative: Logisim-Evolution (free, open-source, runs locally) or EDA Playground (browser-based, supports VHDL and Verilog) with simulation waveform output. Proof artifacts: the logic diagram or HDL description (design artifact) and the truth table and test results (analysis artifact). Verification: a digital electronics engineer reviews the timing analysis — 'what is your setup time margin at this clock frequency, and what happens if it is violated?' — requiring specific reasoning from your own design.