Digital Logic Design

Proof required

Submit: (1) the problem statement with all inputs and outputs defined; (2) the complete truth table; (3) the Karnaugh map with groupings annotated; (4) the minimised Boolean expression derived from the K-map; (5) the gate-level circuit diagram drawn in Logisim Evolution (screenshot or exported image); (6) the Logisim simulation verification — a screenshot showing all rows of the truth table tested, with the output column matching your truth table.

What gets checked

• Karnaugh map groupings are valid — each group must be a power of 2 in size (1, 2, 4, or 8 cells), all cells in each group must be adjacent (including wrap-around), and the groupings must be the largest possible (no group that can be expanded to include another '1' cell without losing adjacency is left unexpanded)
• Minimised Boolean expression is derived from the K-map groupings — each product term in the SOP expression corresponds directly to a named grouping in the K-map; a minimised expression presented without reference to the K-map groupings cannot be verified
• Simulation verification covers all truth table rows — a simulation screenshot that shows only a subset of input combinations has not verified the implementation

Common mistakes

• Deriving a non-minimised expression directly from the truth table and presenting it as 'minimised' — an SOP expression with one term per minterm is a correct but non-minimised implementation; it only qualifies as minimised if a K-map grouping process was applied
• Drawing the gate circuit without simulating it — a gate-level diagram with no simulation verification has not been tested; an implementation error that would be immediately visible in simulation cannot be caught by visual inspection alone

Resources

What a verifier looks for

• Engineering Design Triad: M1 produces a design artifact (gate-level circuit diagram) and an analysis artifact (truth table + K-map + minimised Boolean expression + simulation verification) — both must be present.
• K-map groupings must be valid — check that each group is a power-of-2 size, all cells are adjacent, and no group can be expanded further; invalid groupings produce non-minimal expressions.
• Simulation must cover all truth table rows — check that the simulation screenshot shows all 2^n input combinations (8 rows for 3 inputs, 16 for 4 inputs).
• Minimised expression must be traceable to the K-map groupings — if the expression cannot be derived from the K-map shown, the minimisation step is not demonstrated.
• Reviewer must be an electrical engineer or computer science professional with digital logic design experience — K-map grouping validity and simulation verification require domain-specific expertise.

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Proof required

Submit: (1) the state diagram (as a drawn diagram, not a table — circles for states, labelled arrows for transitions); (2) the state transition table (present state + inputs → next state + outputs + flip-flop excitation inputs); (3) the flip-flop excitation equations derived from the table (using K-maps if there are 3 or more state variables); (4) the Logisim Evolution circuit screenshot showing flip-flops and the combinational excitation logic; (5) a simulation verification screenshot showing the state sequence over at least one full cycle.

What gets checked

• State diagram has one circle per state with transition arrows labelled by both input condition and output — an unlabelled state diagram cannot be used to derive the state transition table and does not satisfy the design artifact standard
• Excitation equations are derived from the transition table with the derivation steps shown — presenting equations without the derivation (no K-map or Boolean manipulation shown) is not a verifiable claim
• Simulation shows the full state cycle — for a counter, every count value must appear in sequence; for a detector, the recognition of the target pattern must be visible; a partial cycle does not verify correct operation

Common mistakes

• Designing a sequential circuit without drawing the state diagram first — the state diagram is the specification of the circuit's intended behaviour; designing the circuit directly in Logisim without a state diagram means there is no specification to verify against
• Using Logisim's built-in counter or shift register component rather than designing from flip-flops and excitation logic — using a built-in component does not demonstrate understanding of sequential logic design; the circuit must be built from individual flip-flops and gates

Resources

What a verifier looks for

• State diagram must be present as a drawn diagram — a table alone is not a state diagram; circles and labelled arrows must be present.
• Excitation equations must be traceable to the transition table — check that the derivation steps are shown, not just the final equations.
• Circuit must be built from individual flip-flops — check that the Logisim screenshot shows flip-flop components, not higher-level sequential library components.
• Simulation must cover a full state cycle — check that the simulation screenshot shows every state in the sequence at least once.
• Reviewer must be an electrical engineer or computer science professional with digital logic/sequential circuit design experience.

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Proof required

Submit: (1) your complete digital logic design report (all sections above, supported by diagrams from M1 and M2); (2) a written record of the reviewer's two technical questions and your responses (200 words minimum, attributing reviewer by professional role and relevant experience).

What gets checked

• Complexity comparison includes specific numbers — 'the combinational circuit requires 5 two-input NAND gates; the sequential circuit requires 3 D flip-flops and 4 two-input gates' — not 'the sequential circuit is more complex'
• Design decision reflection names the alternative specifically and gives a technical tradeoff — 'I used SOP minimisation rather than POS because the number of 1s in the truth table was smaller than the number of 0s, making SOP groupings more compact; POS would produce a correct but longer expression' is a valid reflection
• Reviewer questions show genuine technical engagement — questions like 'why did you choose this flip-flop type?' or 'what would happen if the counter started in an invalid state?' are substantive; 'is this correct?' is not a technical question

Common mistakes

• Omitting the complexity comparison — this section demonstrates that the author can evaluate their own work quantitatively, not just produce it; skipping it converts the report into a lab write-up rather than an engineering design report
• Presenting to a reviewer without digital logic background — the reviewer must be able to evaluate whether the K-map groupings, excitation equations, and state machine design are correct; a general engineer cannot do this

Resources

What a verifier looks for

• Engineering Design Triad check: M1–M3 together produce design artifacts (gate-level circuit diagram + sequential circuit diagram), analysis artifacts (truth table + K-map + excitation equations + simulation verification), and a documentation artifact (design report with complexity comparison and design decision reflection) — confirm all three types are present.
• Complexity comparison must use specific numbers — check that gate counts and flip-flop counts are present, not qualitative comparisons.
• Reviewer questions must be technical and substantive — check that the recorded questions address design decisions, not just factual recall.
• Reviewer must have digital logic or electronics engineering background — K-map validity and sequential circuit correctness require discipline-specific expertise.
• The Proof Accessibility Rule applies — Logisim Evolution is free and open-source; no proprietary EDA tool is required.

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