Digital Logic Design
6 weeks · 0 milestones
Design a digital logic system to implement a defined Boolean function or finite state machine. The system must be non-trivial — at minimum a 4-bit binary counter with enable and reset, an 8-to-1 multiplexer with documented truth table, or an equivalent sequential or combinational circuit. Required documentation: a complete logic diagram or HDL description, a truth table or state transition table, timing analysis identifying critical path and maximum clock frequency (for sequential circuits), and a documented test plan with at least 10 test vectors with expected and actual results. Preferred proof: an FPGA implementation or physical breadboard build with documented test results. Accessible alternative: Logisim-Evolution (free, open-source, runs locally) or EDA Playground (browser-based, supports VHDL and Verilog) with simulation waveform output. Proof artifacts: the logic diagram or HDL description (design artifact) and the truth table and test results (analysis artifact). Verification: a digital electronics engineer reviews the timing analysis — 'what is your setup time margin at this clock frequency, and what happens if it is violated?' — requiring specific reasoning from your own design.
Milestone map
Milestone map
3 milestones
Select or define a combinational logic problem with 3–4 inputs and at least one output — examples include: a 2-bit binary comparator (outputs: A>B, A=B, A<B); a BCD to 7-segment display decoder for digits 0–9; a priority encoder for four interrupt lines; or a majority voting circuit for three sensors. Construct the full truth table. Derive the Boolean expression from the truth table using sum-of-products or product-of-sums. Minimise the expression using a Karnaugh map (3- or 4-variable). Draw the minimised gate-level circuit using standard logic gate symbols. Verify the implementation by simulating it in Logisim Evolution (free, open-source) and confirming that all truth table rows match the simulation output.
Proof required
Submit: (1) the problem statement with all inputs and outputs defined; (2) the complete truth table; (3) the Karnaugh map with groupings annotated; (4) the minimised Boolean expression derived from the K-map; (5) the gate-level circuit diagram drawn in Logisim Evolution (screenshot or exported image); (6) the Logisim simulation verification — a screenshot showing all rows of the truth table tested, with the output column matching your truth table.
What gets checked
- Karnaugh map groupings are valid — each group must be a power of 2 in size (1, 2, 4, or 8 cells), all cells in each group must be adjacent (including wrap-around), and the groupings must be the largest possible (no group that can be expanded to include another '1' cell without losing adjacency is left unexpanded)
- Minimised Boolean expression is derived from the K-map groupings — each product term in the SOP expression corresponds directly to a named grouping in the K-map; a minimised expression presented without reference to the K-map groupings cannot be verified
- Simulation verification covers all truth table rows — a simulation screenshot that shows only a subset of input combinations has not verified the implementation